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VHDL-2008: Just the New Stuff (Systems on Silicon), by Peter J. Ashenden, Jim Lewis
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VHDL-2008: Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware description language. Written by the Chair and Technical Editor of the IEEE working group, the book is an authoritative guide to how the new features work and how to use them to improve design productivity. It will be invaluable for early adopters of the new language version, for tool implementers, and for those just curious about where VHDL is headed.
* First in the market describing the new features of VHDL 2008;
* Just the new features, so existing users and implementers can focus on what's new;
* Helps readers to learn the new features soon, rather than waiting for new editions of complete VHDL reference books.
* Authoritative, written by experts in the area;
* Tutorial style, making it more accessible than the VHDL Standard Language Reference Manual.
- Sales Rank: #1973481 in eBooks
- Published on: 2007-11-26
- Released on: 2007-11-26
- Format: Kindle eBook
- Number of items: 1
About the Author
Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.
Most helpful customer reviews
2 of 2 people found the following review helpful.
Great intro
By wiredweird
As the title says, this presents only the deltas from the previous version of the spec. If you're not already reasonably conversant with VHDL, this won't do a thing for you. But, if you've used VHDL long enough to be utterly maddened by some of its shortcomings, get this one. You're in for some happy surprises.
The two biggest changes have to do with generics and with assertions. Since day one, logic designers have treated strongly-typed VHDL as an untyped language. We've had to cast everything to bitvectors, like a PL/I programmer who uses unspec for everything, because of inflexible typing. A FIFO, for example, that handled one data type could never be reused with a different type. You'd have rewrite the entire FIFO, identical in every way, except for the data type. Yuk - better to cast everything to std_logic_vector, reuse the component, and adopt the old C-language slogan: "strong typing is for weak memories." Generic types, more like C++ templates, get past that. Generic subprograms increase reusability, too. If you're new to the concept, it's like passing a function as parameter, but at compile time. In the world VHDL addresses, compile-time binding is just fine.
Much has been made of SystemVerilog assertions - and with good reason. They add a huge level of expressiveness to the verification engineer's task, and represented a real advance over what VHDL had. The gap closes with VHDL's integrated PSL. I haven't done a point by point comparison, but SV assertions and PSL appear to have closely comparable feature sets. That includes Verilog's scope-busting ability to reach internal signals deep down in the structure hierarchy, but PSL allows up-level references, too.
VHDL 2008 also includes minor features that scratch many itches from the previous standards: ability to use std_logic values as "if" tests without casting to boolean, conditional assignments in sequential blocks, bitwise reduction operators, and fixes to other niggling annoyances that people have been coding around for years.
The one thing conspicuous by its absence is mention of what's in the synthesizable subset. Using advanced features in testbenches is nice. But, if you can't put them in the payload logic, they tend to create impedance mismatch where the application plugs into the test harness. Also, one of VHDL's big advantages has been its formally standardized synthesizable subset. That meant you could code for one tool suite and have some assurance that your work would port to other tools, too. Without that kind of contract for reusability, the new features (especially richer generics) will never live up to their promise.
This book is just a stopgap, and will become obsolete once complete VHDL references include the new features. Those books aren't out yet, however, and this is. For now, I recommend this highly to anyone who uses or develops VHDL tools.
-- wiredweird
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